1. Field of the Invention
The invention relates in general to systems for generating layouts for integrated circuits (ICs) and in particular to an automated layout system for analog ICs.
2. Description of Related Art
A circuit designer typically creates an IC design in the form of a netlist referencing circuit devices to be included in the IC and indicating which conductive net is to be connected to each device terminal. A digital IC designer usually processes a netlist description of an IC using a placement and routing (P&R) tool that automatically generates an IC layout indicating the position and orientation of each device within the IC and indicating how conductors forming nets interconnecting device terminals are to be routed within the IC. When generating a layout for a digital IC, the P&R tool treats each device as a separate cell having a predetermined internal layout. The tool iteratively repositions cells and reroutes nets until it arrives at a layout solution satisfying constraints on the size and aspect ratio of the available layout area, on signal path delays, on net widths and spacing, and on power density and other constraints.
Although automated placement and routing tools are widely used for generating digital IC layouts, they are not often used to generate analog IC layouts. A typical analog IC includes circuits formed by transistors and passive devices that must be laid out in particular patterns in order for the circuits to behave properly. For example a pair of transistors forming a differential pair circuit must be closely matched and the differential pair circuit they form must have a symmetric layout in order to properly balance the differential currents they convey. To create a layout for a differential pair circuit, it is not sufficient to merely select a separate layout for each transistor, place each transistor near one another and then route nets interconnecting them. It is necessary to generate a detailed layout for the differential pair circuit as a whole, wherein the gate, drain and source components of the two transistors are appropriately matched and symmetrically distributed and interconnected. Since placement and routing algorithms developed for digital circuits are not adapted for satisfying matching and symmetry constraints and other constraints on analog circuit layouts, designers often resort to manually producing layouts for analog ICs, or for the analog portions of mixed-signal ICs, even though handcrafted layouts can be time-consuming and error-prone.
In the past decade, academia and industry have proposed both “template-driven” and “constraint driven” automated placement and routing tools for analog circuits, but the drawbacks to these systems have prevented them from being widely used. A template-driven automated layout system generates an IC layout by processing a netlist to determine whether any portion of an analog circuit it describes can fit into any one of a set of pre-designed handcrafted layout templates. Each template specifies a complete layout for a separate analog circuit such as for example a current mirror or a differential pair. Although this approach is usually fast and easy and can produce a compact layout when suitable templates are available, it lacks flexibility because it does not allow a layout designer to easily vary the layout from design-to-design when differences in layout constraints require small variations in circuit layout. For example although two current mirror circuits may be schematically similar, they cannot be laid out according to the same layout template if the current mirror circuits require transistors of differing in-factor (i.e. having differing numbers of gate fingers). Even though a designer may have previously generated a template for a current mirror using in-factor 1 transistors, the designer must manually generate another template for a schematically similar current mirror using in-factor 2 transistors. Also though two circuits are schematically similar and are formed of transistors having the same in-factor, they cannot use the same layout pattern if they are subject to differing technology constraints. Differences in technology constraints can also influence device group a layout pattern. The nets that interconnect elements of the various devices of a circuit are subject to width and spacing constraints that can vary from one IC to another depending on the fabrication technology used to make the IC. Thus the number of templates needed to enable a template-based P&R tool to layout an analog ICs having a wide variety of circuits and subject to a wide variety of constraint without much human intervention would be prohibitively large.
A constraint-driven automated layout tool generates an IC layout satisfying various constraints on the layout, including device matching and symmetry constraints, without using predetermined layout templates. FIG. 1 shows the general flow of a typical prior art constraint-driven layout tool. The tool initially analyzes input data 10 including a netlist, a circuit performance specification and technology file to identify groups of devices that are subject to device and net matching and symmetry constraints (step 12). The tool creates a database 14 indicating the constraints on each device or device group and then generates a layout for each device or device group that satisfies all device matching and symmetry constraints (step 16) in database 14. The tool then places the device and device group layouts generated at step 16 in the IC layout and routes the nets interconnecting the device terminals (step 18) to produce a final layout 20. Although the constraint-driven approach is more flexible than the template-driven layout approach, the resulting layout 20 is often not as good in many respects as handcrafted and template-driven layouts.
What is needed is a flexible automated placement and routing system for an analog or mixed signal circuit that can generate high-quality layouts.